CV

Education

• Ph.D in Hong Kong University of Science and Technology
• Mphil. in Hong Kong University of Science and Technology, 2020
• B.S. in Hefei University of Technology, 2016

Work experience

• 2021 - Now: Huawei Hong Kong Research Center
  • Processor Lab/Davinci AI Core Department
  • Role: Senior Digital Design Engineer
• 2020 - 2021: Integrated Circuit Design Center, HKUST
  • Role: Digital Design Engineer
  • Duties: Designed and sign-off an embedded cipher using Verilog with TSMC 65nm library. Responsible for the whole digital IC flow including the cipher algorithm design, Verilog design, DC synthesis, timing closure, P&R, PTPX power analysis, clock tree synthesis and DRC/LVS check
• 2018 - 2019: Hong Kong Applied Sci. & Tech. Research Institute
  • Role: FPGA Engineer
  • Duties: Proposed, designed and implemented a nested Winograd AI accelerator on VC709 and ZCU102 FPGA platform. The hardware part is implemented with a mixture of HLS and Verilog. The accelerator supports out-of-order execution of the Winograd, Conv2D, Gemm, Quantization, etc. CISC-like instructions and synchronized the data through several on-chip memories. The firmware is implemented in the Xilinx software development kit and communicated with VC709/ZCU102 through PCIE3.0 and AXI-bus. The instruction-level parallelism is carefully designed to hide the communication time.

Skills

• Verilog, System Verilog
• C++
• Python
• Professional Skills
  • RTL Design
  • Modeling
  • Optimization Algorithm

Service and leadership

• Mentoring graduate students